[072] Point-Of-Load Converter Design - Part I Loop Gains and Step Loads

Point-of-load converter loops need to measured as they push the state-of-the-art in crossover frequencies.


Recent changes in component technologies have led to point-of-load power converters that are pushing the boundaries of control-loop performance. The need to break open and measure the loop is more essential now than ever before if lifetime system stability is to be guaranteed.

High-Frequency Point-of-Load Buck Converters

There has always been a debate about how essential it is to measure the loop of a switching power supply. Some power designers have always resisted this part of development and design validation, claiming they are able to tune a loop properly through step-load testing [1]. While this may have worked with low performance power supplies, it is increasingly difficult with modern high-performance systems

Seven things have happened in recent years that have brought the loop testing issue back to the forefront. These issues combine to create a much higher risk of power supply instability.

  1. Power converter switching frequencies have been raised significantly to 2 MHz or more.
  2. Multiple point-of-load power supplies are incorporated on a single electronics assembly
  3. Input and output capacitors are comprised of just multilayer ceramics with negligible ESR
  4. Each converter minimizes the output capacitance to reduce board area
  5. Loop gains have become very aggressive in order to meet step-load requirements
  6. Some or all of the power supply compensation is internal to the integrated power supply
  7. Voltage-mode control is being used in place of current-mode control

Most application notes for these supplies tend to imply that their design is straightforward, and no more complicated than putting a linear regulator on the board. This can get many system designers into trouble. Now let’s look at each of these seven risk issues.

1. High Switching Frequencies

Switching frequencies have risen substantially in the last 10 years as more and more regulators are forced onto boards in close proximity to the processors that they are supplying. 100 kHz switching is no longer sufficient since it results in large inductors and capacitors that simply won’t fit in the space available.

As switching frequencies climb, much greater demands are placed upon feedback amplifiers and layout. Both the power stage and feedback networks can exhibit small-signal and large-signal behaviors that are not accurately predicted by the modeling.

2. Multiple Converters on Assembly

With so many regulators on a board, the probability of a marginal design increases. Furthermore, proper testing of each regulator can seem daunting and overly time-consuming. If the makers of the parts do not suggest loop gain testing, it is unlikely than non-power engineers will even consider doing any. And when the power supplies are designed into the boards, there are usually no provisions made for loop. This can either increase the difficulty of test, or sometimes render it impossible when traces are placed in inner layers that are not accessible.

3. Multilayer Ceramic Capacitors

Multilayer ceramic capacitors have extremely low esr values, and very little capacitance is needed to meet output ripple requirements. Hence the power supply makers can minimize the design area, leaving it up to the electronics assembly designer to add more capacitance as needed. On the input side of the converter, if additional filtering is used for noise attenuation, a series inductor can resonate with the low-esr capacitors to form a peak in filter output impedance. This can lead to classic input filter oscillation issues [2].

4. Minimum Output Capacitance

As the output capacitance reduces, the converter is far more sensitive to capacitive loading. In the earlier days of power supply design, the capacitance in the converter would dominate any loading capacitance, making the loop response relatively impervious to any additions. This is no longer true, and local bypass capacitance at the load can be significantly larger than the power supply capacitance for which the loop has been optimized.

5. Aggressive Loop Gains

Most power supplies in the past would have loop gains which were very conservative. It is not unusual to find a crossover frequency of just 1 kHz or less for a 100 kHz converter. This is rapidly changing for point-of-load converters. It is not uncommon now to find loop gains well in excess of 1/10 the switching frequency. As this crossover frequency increases, the power stage models become less reliable, and the measured response does not follow theory so closely. Also, with high crossover frequencies, the gain-bandwidth of the error amplifier becomes a limiting factor.

It is essential to verify these more aggressive loops if long-term instability is to be avoided.

6. Internal Compensation

Many of the new low-power switching regulators remove the burden of compensation from the user, and they include the compensation components inside the IC. This can either be just the feedback compensation components R2, C1 and C3 shown in Figure 1, or it can include the input compensation components R1, Rb, C2 and R3 as well.

The problem with this integrated approach is that the compensation components are optimized for an assumed value of L and C in the power stage. If these values change, as is almost always the case, there is no opportunity for the user to properly compensate the power stage to achieve the best loop design.

7. Voltage-Mode Control

The great benefits of current-mode control are adaptivity to the inductor value, elimination of the LC filter resonance, and naturally optimal control in either CCM or DCM regions of operation. The main downside of current-mode has always been difficulty of implementation due to worsened signal-to-noise ratios in the modulator. This last problem is exacerbated as frequencies climb, so many integrated power supply makers have reverted back to voltage-mode control. This brings back in all of the lack of adaptivity of the loop design, and the loop gain and phase margin are much more susceptible to component variation.

In the rest of this article, we will look at how the output capacitor size interacts with loop bandwidth and the output step-load response


Effect of Capacitance on Step-Load Response

Figure 1 shows the schematic of a buck converter with a synchronous rectifier and MLC output capacitor.

fig 1

Figure 1: 400 kHz Buck Converter with Synchronous Rectifier and MLC Output Capacitor. Output voltage is 1.2 V at 20 A. Input Voltage is 12 V.

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